As semiconductor devices, including integrated circuits (IC), operate at higher frequencies, higher data rates, and lower voltages, the ability to limit noise in the power and ground (return) lines and supply sufficient current to accommodate faster circuit switching become increasingly important. In order to provide low noise, stable power to the IC, impedance in conventional circuits may be reduced by the use of additional surface mount technology (SMT) capacitors interconnected in parallel. The higher operating frequencies (higher IC switching speeds) mean that voltage response times to the IC must be faster. Lower operating voltages require that allowable voltage variations (ripple) and noise be reduced. For example, as a microprocessor IC switches and begins an operation, it calls for power to support the switching circuits. If the response time of the voltage supply is too slow, the microprocessor will experience a voltage drop or power droop that will exceed the allowable ripple voltage and noise margin and the IC will malfunction. Additionally, as the IC powers up, a slow response time will result in power overshoot. Power droop and overshoot must be controlled within allowable limits by the use of capacitors that are close enough to the IC so that they provide or absorb power within the appropriate response time.
SMT capacitors for impedance reduction and dampening power droop or overshoot are generally placed on the surface of the board or semiconductor package as close to the IC as possible to improve circuit performance. Conventional designs have capacitors surface mounted on a printed wiring board (PWB) or semiconductor package clustered around the IC. Large value capacitors are placed near the power supply, mid-range value capacitors at locations between the IC and the power supply and small value capacitors very near the IC. Large numbers of SMT capacitors, interconnected in parallel, are often required to reduce power system impedance requiring complex electrical routing. This leads to increased circuit loop inductance, which in turn increases impedance, constraining current flow, thereby reducing the beneficial effects of the surface mounted capacitors. As frequencies increase and operating voltages continue to drop, increased power must be supplied at faster rates requiring increasingly lower inductance and impedance levels.
Considerable effort has been expended to minimize impedance. U.S. Pat. No. 5,161,086 to Howard, et al., for example, provides one approach to minimizing impedance and “noise”. Howard, et al. provides a capacitive printed circuit board with a capacitor laminate (planar capacitor) included within the multiple layers of the laminated board, a large number of devices such as integrated circuits being mounted or formed on the board and operatively coupled with the capacitor laminate (or multiple capacitor laminates) to provide a capacitive function employing borrowed or shared capacitance. However, such an approach does not necessarily improve voltage response. Improved voltage response requires that the capacitor is placed closer to the IC. However, simply placing the capacitor laminate closer to the IC may not be sufficient because the total capacitance available may be insufficient.
U.S. Pat. No. 6,611,419 to Chakravorty provides for an alternate approach to embedding capacitors to reduce switching noise wherein the power supply terminals of an integrated circuit die can be coupled to the respective terminals of at least one embedded capacitor in a multilayer ceramic substrate.
U.S. Provisional Patent Application Nos. 60/637,813, 60/637,813, and 60/637,817 provide for power supply cores for ICs, consisting of embedded discrete ceramic capacitors and planar capacitors. U.S. Provisional Patent Application No. 60/692,119 describes a discrete embedded ceramic capacitor design and method of making thereof whereby the screen-printed copper electrode completely encapsulates the screen-printed dielectric thus resulting in improved mechanical reliability and larger capacitor area compared to earlier designs.
The instant invention provides a novel low inductance capacitor and interconnect design utilizing the capacitor type described above, for interconnect to the IC thus reducing needed capacitance and enabling rapid charge supply and clean power supply to the IC from the embedded capacitors.
A primary major source of inductance of an embedded capacitor is related to the vias or wires or connection paths by which the capacitor connects to the system. A typical embedded capacitor without multiple vias has inductance ranging from hundreds of pico-henries to nano-henries. In certain applications, it can be so large that the first resonant frequency in the package impedance profile is forced into the low frequency range (<100 Mhz). Current connection designs for embedded capacitors are typically a pair of single vias, which connect to the electrodes separately. These vias can be located on any position of the electrode. The length of these vias is usually tens of micrometers for blind micro-vias to hundreds of micrometers for through hole via types. In certain situations, the inductance presented by the vias can be larger than the inductance presented by the capacitor; thus the vias become the major component in limiting the frequency response of the embedded capacitors. Therefore, reduction of the via inductance is critical to improving the performance of the capacitors.
To reduce the connection inductance, vias must be close to each other. Theoretically, the closer the vias are, the lower the inductance will be. However, since there must be a clearance between via landings due to capacitor designs and process limitations, the vias consequently have to be separated by a certain distance. These factors typically drive the inductance down below a hundred pico-henries, but further impedance reduction is desirable.
Embodiments of the invention described below provide improved capacitors for reducing total inductance in electronic IC packages and methods for making them.